1. Field of the Invention
This invention relates to integrated circuit manufacture and, more particularly, to transistors formed on separate elevational levels and an interconnect routed between source and substrate regions on the upper level transistor to a drain of the lower level transistor to configure a high performance, high density integrated circuit.
2. Description of the Relevant Art
The structure and the various components, or features, of a metal oxide semiconductor (xe2x80x9cMOSxe2x80x9d) are generally well known. A MOS transistor typically comprises a substrate material onto which a patterned gate conductor is formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source/drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS (NMOS) transistor employs n-type junctions placed into a p-type substrate. Conversely, a typical p-channel MOS (PMOS) transistor comprises p-type junctions placed into an n-type substrate. The substrate comprises an entire monolithic silicon wafer, of which a portion of the substrate known as a xe2x80x9cwellxe2x80x9d exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposing junctions in the non-well areas. Accordingly, wells are often employed when both n-type and p-type transistors (i.e., CMOS) are needed.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductor, source/drain junctions, and interconnect to the junctions must be as small as possible. Many modern day processes employ features which have less than 1.0 xcexcm critical dimension. As feature size decreases, the resulting transistor as well as the interconnect between transistors also decrease. Smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
The benefits of high density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the lower resolutions needed for submicron features. To some extent wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
There are many numerous other techniques used to achieve a higher density circuit, however, these techniques as well as others still must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot in all instances offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects (xe2x80x9cSCExe2x80x9d) generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive subthreshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection (xe2x80x9cHCIxe2x80x9d). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric field can give rise to so called hot carriers and the injection of those carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since those carriers can become trapped and skew the turn-on voltage of the ensuing transistor.
It appears as though even the most advanced processing techniques cannot avoid in all instances the problems which arise as a result of high density fabrication. As features are shrunk and are drawn closer together across a single topological surface, the closeness of those features causes numerous problems even under the most advanced processing conditions. It therefore appears that there may be a certain limitation beyond which feature sizes cannot be reduced if those features are to reside on the single elevational level. It would therefore be desirable to derive a processing technique which can produce features on more than one level. That is, it would be beneficial that this multi-level processing technique produce both active (transistors) and passive (capacitors, resistors, etc.) in three dimensions so as to enhance the overall circuit density without incurring harmful side effects associated with feature shrinkage and closeness.
Before a three-dimensional, multi-level transistor fabrication process can be introduced, however, the process must pay careful attention to the interconnection between transistors placed on separate levels. Therefore, it is desirable to derive an interconnect scheme which can connect various features on one elevation (topological) level to features on another level. That interconnection must be as short as possible in order to minimize resistance in critical routing conductors between transistors. The desired fabrication process must therefore incorporate not only multi-level fabrication but also high performance interconnect routing as an essential part of that process.
Most logic block portions of an integrated circuit comprise transistors interconnected in various ways. For example, combinatorial logic includes, for example, NAND gates and NOR gates. Both NAND and NOR gates include series-connected transistors. More specifically, the source-drain paths of two or more transistors are connected in series between a power conductor and an output node. An example of a two-input NAND gate is shown in FIG. 1 as reference numeral 10. FIG. 2 illustrates a counterpart two-input NOR gate 12. NAND gate 10 includes a pair of n-channel transistors 14 and 15 connected in series between a ground terminal and an output Q. NOR gate 12 includes a pair of p-channel transistors 18 and 20 connected in series between a power supply and output Q.
The series-connected between two or more transistors, regardless of whether the transistors are n-channel or p-channel, presents a unique set of problems. For example, parasitic capacitance 22a and 22b is attributed to the connection between a source junction of one transistor and a drain junction of another transistor.
Parasitic capacitance 22 is the normal response of voltage placed upon a diffused junction area. Whenever the junction is coupled separate from the substrate (or xe2x80x9cbodyxe2x80x9d), capacitance occurs therebetween. More importantly, a voltage difference arises between the junction and substrate, often referred to as the xe2x80x9cbody effectxe2x80x9d. Body effect is the term given to the modification of threshold voltage, demonstrated as a voltage difference between the source and substrate areas. In the example provided, n-channel transistor coupled at output Q will switch slower if the transistor source potential is not the same as the substrate. In most instances, the substrate will be coupled to power/ground, leaving the source of transistor 14 floating dissimilar from ground. To illustrate how the body effect changes the threshold voltage of transistor 14, it is recognized that voltages at the input of nodes A and B may be selected such that voltage on capacitor 22a is charged. If the inputs are then set to a logic 1, the source terminal of transistor 14 will transition to a voltage of Vcc minus a threshold voltage. Thus, transistor 16 will have to discharge the source node associated with capacitor 22a in order to turn on transistor 14. In summary, body effect implies the fall time of transistor 14 will be slower than transistor 16. The converse applies to the transistors 18 and 20 of FIG. 2.
To minimize the body effect, it is important to minimize capacitance at the internal nodes of series-connected transistors. FIGS. 1 and 2 depict only a two-input gate structure; however, it is recognized that more than two inputs and therefore more than two series-connected transistors may be used in many logic designs. The body effect is exacerbated with the addition of transistors coupled in series. Many design strategies are to place transistors with the latest arriving signals nearest the output Q of the series-connected transistors. The early signals in effect xe2x80x9cdischargexe2x80x9d internal nodes attributed to parasitic capacitance 22. The late arriving signals therefore have the parasitic capacitance of that node discharged with minimum body effect. Another, more workable strategy is to couple the source node to the substrate or body.
FIG. 3 illustrates a series-connected set of transistors. The transistors are shown as n-channel transistors; however, p-channel transistors may equally and alternatively be employed. Series-connected transistors 24, 26 and 28 are shown connected between a power/ground supply and an output node Q. The technique for minimizing parasitic capacitance and body effect deals principally with connecting source S terminal of transistor 26 to the substrate (i.e., body) B, and also connecting the source S of transistor 28 to body B. It may not be necessary, however, to connect the source and body of transistor 24; it is more important to connect the internal source nodes of transistors 26, 27, etc.
Referring to FIG. 4, a conventional manner for coupling source and substrate/body regions is shown. In particular, FIG. 4 illustrates a transistor (either transistor 14 or transistor 20 shown in FIGS. 1 and 2). Arranged on one side of a gate conductor 30 is a source region 32. Source 32 may extend to the lateral boundary of a metal conductor 34. Metal conductor 34 includes a series of contacts 36 which extend from conductor 34 downward to source 32. Conductor 34 may extends laterally from source 32 to an implant region of a type dissimilar from source 32. The latter implant is known as a well implant, and is indicated as reference numeral 38. Well implant 38 matches the implant dopant used for the substrate, opposite the source/drain implant. Well implant 38 electrically receives coupling from conductor 34 via contacts 40.
FIG. 4 illustrates transistors 14/20 formed upon a single elevation level and, more importantly, the additional space requirements needed to accommodate source-to-substrate connection. That space requirement is primarily mandated by the additional well implant 38, and the spacing needed between well 38 and source/drain implant 32. Thus, while it is beneficial to couple the internal source node to a substrate, the costs involved with that coupling is demonstrated mostly in terms of additional layout space.
It would be desirable to derive a manufacturing process which can reduce the body effect by mutually connecting the source junction to the body whenever series-connected transistors are encountered. It would be further desirable to perform the interconnection as a multi-level processing technique. More specifically, an advancement may be made if the source and body connection of one transistor can be further connected to a drain of another transistor, both transistors of which are arranged on separate elevation levels. The improved interconnect scheme is one having limiting routing. A relatively short source-substrate-drain interconnect has minimum resistance, capacitance and inductance, the result of which is a high performance, high density integrated circuit.
The problems outlined above are in large part solved by a multi-level transistor fabrication technique. The present technique can produce one or more active or passive devices on a first level, followed by one or more active or passive devices on a second level. The first level is substantially planar and extends across an entire wafer surface. The second level is also substantially planar and parallel to the first level, but spaced by a dielectric therefrom.
According to a preferred embodiment, the multi-level transistor fabrication technique is suitable for producing at least one transistor on the first level and at least one transistor on the second level. The first and second level transistors each comprise respective source and drain regions. The source region of the first transistor is connected to the drain region of the second transistor to form a series-connection. An interconnect is used to form the series connection. Coupled between the interconnect and the respective source and drain junctions may be a silicide. The interconnect may extend from the drain region of a first transistor upward to a source region of a second transistor. Interconnect therefore extends across an interlevel dielectric which separates the first and second transistors. The interconnect may further extend in a lateral direction from the source of the second transistor to the substrate of the second transistor. Resulting from the way in which the second transistor is confined within a localized substrate, interconnection between the source and substrate of the second transistor can be relatively short.
The process of forming the first and second transistors on separate elevation levels, and interconnecting a drain of the first transistor to a source of the second transistor is replicated and equally applicable to numerous other transistors arranged on the first and second levels. Thus, according to a preferred embodiment, there may be more than two transistors connected in series, and more than two separate elevation levels needed to accommodate more than two series-connected transistors.
By interconnecting two or more series-connected n-or p-channel transistors, the present technique is applicable to any logic block which requires series-connection. For example, the present process is applicable to series-connected transistors in NAND gates and/or NOR gates. More importantly, however, is the relatively short interconnection used to link a source of one transistor to a drain of another. Equally important is the short interconnection between the source of one transistor to the substrate of that transistor. Source-to-substrate connection is carried out without having to form an independent well region, and spacing of that well region from the source/drain implant area. As such, the lateral dimension of a transistor having source-to-substrate connection is relatively small. This not only allows high density integrated circuits, but also implements short interconnect with minimum resistive, capacitive, and inductive loading.
Broadly speaking, the present invention contemplates forming a pair (or more) of transistors having source/drain paths of each transistor connected in series to a power supply. A first transistor of the pair is provided having a first gate conductor arranged upon a first substrate between a first source implant and a first drain implant. An interlevel dielectric is deposited upon the first source implant, upon the drain implant and upon the first gate conductor. A second substrate is then formed within the interlevel dielectric a spaced distance above and laterally offset from at least a portion of the first gate conductor. A conductive plug is formed through the interlevel dielectric to the first drain implant. The conductive plug abuts a lateral surface of the second substrate. A second transistor of the pair is then formed having a second gate conductor arranged upon the second substrate between a second source implant and a second drain implant. The second source implant is proximate to the conductive plug. An interconnect is patterned across a portion of the second substrate in electrical communication with both the second substrate and the second source.
Preferably, a portion of the interconnect is patterned upon the plug. The combination of interconnect and plug forms a relatively short conductive path between the interconnected-coupled source and substrate of the second transistor to the drain of the first transistor.
The second substrate is preferably formed within a localized region of the interlevel dielectric. Specifically, the second substrate is brought about by etching a trench into the interlevel dielectric upper surface, and then filling the trench with preferably a polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) material. Polysilicon material is rendered conductive by doping it with either an n-type or p-type species.
The conductive plug is formed by etching an opening through a portion of the interlevel dielectric to the first drain. The opening extends perpendicular to the drain upper surface and selective to interlevel dielectric. Interlevel dielectric is removed from a sidewall surface of a polysilicon substrate. The sidewall surface, however, is doped with a source implant. When the opening is filled with a conductive material, the sidewall surface and, more specifically, the source region of the second transistor is coupled with the drain of the first transistor.
The present invention further contemplates a series-connected pair of transistors. The pair of transistors comprises a first transistor and a second transistor. The second transistor is arranged upon and within a second topography extending a dielectric distance above the first transistor topography. A first conductive element is configured from a lateral surface of the second transistor source to an upper surface of the first transistor drain. Likewise, a second conductive element is configured from the second transistor source to an upper surface of the second topography.
Preferably, the second topography comprises a substrate into which the second source and drain regions are laterally bound. The second topography comprises an isolated region of polysilicon containing the entirety of the second source and drain implant regions.